As conventional semiconductor devices become faster, impedance matching may be more difficult. For example, when a conventional semiconductor device outputs/receives data to/from an external device at a relatively high speed, a reflected wave may be generated. The reflected wave may result from mismatched impedance between signal lines and/or a signal line and an output driver. The reflected wave may cause distortion of transmitted data, leading to errors. Matching impedance may suppress and/or prevent generation of the reflected wave when transmitting data.
To suppress the mismatched impedance, a conventional semiconductor device may have an off chip driver (OCD) and an on die termination circuit (ODT). The OCD may output a signal to the external portion. The on die termination circuit (ODT) may suppress and/or prevent reflection of a signal transmitted from the external circuit. In this example, the impedance characteristics of the OCD or ODT may be calibrated to secure signal integrity. As conventional semiconductor devices operate at higher speeds, the need for calibration of the impedance characteristics increases.
The OCD and/or ODT, however, may operate many switches simultaneously, which may generate noise during the calibration procedure. The amount of total electric current consumed by the OCD may change according to a value of data output from the conventional semiconductor device. Such a change in the amount of electric current may generate an induced electromotive force due to a parasitic inductance in a power line for supplying power to the OCD. The induced electromotive force may also be generated in the ODT, and may cause noise, reduce a voltage and/or time margin of a signal to restrict operating speed of the semiconductor device.
Conventionally, the OCD and ODT may use a differential signal in which a constant current is consumed. To use a differential signal, however, the number of terminals required for transmitting data is twice that of when a single signal is used. For example, when data output from the semiconductor device is 8-bit data, if a single signal is used, 8 output terminals are needed, whereas if a differential signal is used, 16 output terminals are needed.
Conventionally, to suppress degradation of system performance due to noise, a semiconductor device performs low weight coding using a data bus inversion circuit. When data are subjected to the low weight coding, the amount of the electric current flowing through data I/O line of the semiconductor device is reduced, such that bandwidth of data I/O line may be improved and/or data skew may be reduced.
Conventionally, a majority voter circuit may be used to perform low weight coding. A conventional majority voter circuit compares the number of bits having a value of “0” and the number of bits having a value of “1” in the data to determine which type of bit is a majority.
FIG. 1 is a block diagram illustrating a conventional data bus inversion circuit.
Referring to FIG. 1, a data generating portion (not shown) of a system including a semiconductor device may output data Data and inverted data /Data. A majority voter circuit 10 may receive the data Data and the inverted data /Data and determine which bit is in a majority from the data Data based on the number of bits having a value of “0” and the number of bits having a value of “1”. The majority voter circuit 10 may generate and output a selecting signal sign based on which type of bit is in the majority.
For example, when the data Data is 8-bit data, the majority voter circuit 10 may compare the number of “0”s and the number of “1”s within the 8-bit data Data. If the number of “0”s is greater than 4 the majority voter circuit 10 outputs a selecting signal sign having an “L” level. Alternatively, if the number of “0”s is less than 4, the majority voter circuit 10 outputs a selecting signal sign having an “H” level.
An encoder 20 may select either of the data Data or the inverted data /Data in response to the selecting signal sign applied from the majority voter circuit 10 to output low weight coding (LWC) data.
Assuming data having “0” as a majority bit-type is easier for the system to increase a bandwidth and 8-bit data are applied, when the number of bits having a value of “0” is more than the number of bits having a value of “1” (e.g., Data of “00100100”), the majority voter circuit 10 may output the selecting signal sign having an “L” level such that the data Data may be output from the encoder 20. On the other hand, when the number of bits having a value of “1” is greater than the number of bits having a value of “0” (e.g., Data of “11100110”), the majority voter circuit 10 may output the selecting signal sign having an “H” level such that the inverted data /Data obtained by inverting the data Data may be output from the encoder 20 to make the number of bits having a value of “0” more than the number of bits having a value of “1” like “00011001”.
FIG. 2 is a circuit diagram illustrating a conventional majority voter circuit. The majority voter circuit of FIG. 2 is an analog majority voter circuit and differential amplifier.
Referring to FIG. 2, an NMOS transistor N1 activates the majority voter circuit in response to an enable signal En. The enable signal En may be applied while the system receives the data Data and the inverted data /Data, or alternatively, the enable signal En may be applied invariably. A plurality of NMOS transistors NL0 to NL7 and NR0 to NR7 constitute an input portion of the majority voter circuit. The NMOS transistors NL0 to NL7 may receive corresponding bits D0 to D7 of the data Data, and the NMOS transistors NR0 to NR7 may receive corresponding bits /D0 to /D7 of the inverted data /Data. The NMOS transistors NL0 to NL7 and the NMOS transistors NR0 to NR7 may generate a voltage difference between a first node Node1 and a second node Node2 in response to the input data Data and the inverted data /Data.
Two PMOS transistors P1 and P2 may function as an amplifying circuit. The amplifying circuit may detect and amplify the voltage difference between the first and second nodes Node1 and Node2. The selecting signal sign may be output as a voltage level of the second node Node2.
For example, the conventional majority voter circuit of FIG. 2 detects and amplifies the voltage difference between the data Data and the inverted data /Data input via the NMOS transistors NL0 to NL7 and NR0 to NR7, respectively, to output the selecting signal sign. However, when the number of bits having a value of “0” is equal to the number of bits having a value of “1”, a voltage difference between the ends of the differential amplifier may not exist, and thus, determining a majority may be impossible.
To compensate for such errors, two dummy transistors DNL and DNR may be employed in the majority voter circuit of FIG. 2. A weight applied using the dummy transistors DNL and DNR may be, for example, 0.5 or 1. When a weight is applied using the dummy transistors DNL and DNR, a ratio difference between the ends of the input portion is about 5.88% ( 0.5/8.5) when a weight of 0.5 is applied, and about 11.1% ( 1/9) when a weight of 1 is applied. The greater the difference between the ends of the input portion, the more stably the system may operate. Even though a weight is applied using the dummy transistors DNL and DNR, however, errors in determining a majority of data due to, for example, data distortion caused by noise, mismatched impedance with the external device, a difference in threshold voltage or a difference in size of the transistor may still occur.